The present invention relates to methods for generating timing constraints of logic circuits and particularly to a method for generating a timing constraint on a higher-level block in hierarchical design without an error.
With recent miniaturization in semiconductor fabrication processes, logic circuits to be designed have become larger in scale and more complicated. Therefore, hierarchical design in which a logic circuit to be implemented is divided into a plurality of partial circuits each having a specific function and the partial circuits are designed in parallel has been adopted in most cases.
FIG. 3 illustrates an example of a hierarchically designed logic circuit. A highest-level block 31 represents a whole logic circuit to be designed and includes circuit blocks 32 and 33 respectively representing partial circuits. The circuit block 32 includes circuit blocks 34 and 35 respectively representing partial circuits. The circuit block 34 includes primitive circuits 36, 37 and 38 and is at the lowest level.
Timing design of a logic circuit is generally carried out by using a logic synthesis tool, a logic optimization tool, a timing analysis tool and other tools and needs circuit constraints that define circuit specifications to be implemented. These circuit constraints include a timing constraint such as a constraint defining a signal transmission time from an element in a circuit to another element to be connected thereto.
In performing timing designs on blocks at respective levels in a hierarchical structure, a timing constraint is required for each block. If a whole logic circuit is to be designed, a timing constraint on the highest-level block is generated. The timing constraint on the highest-level block is generated by a designer based on circuit specifications. In general, timing constraints on lower-level blocks are repeatedly generated based on the timing constraint on the higher-level block, thereby designing a desired logic circuit. Such a technique is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 10-187787, for example.
In addition to the technique of generating timing constraints on lower-level blocks based on a timing constraint on a higher-level block described above, a technique of generating a timing constraint on a higher-level block based on existing timing constraints on lower-level blocks has been proposed to share design resources. This technique is often adopted for an SOC design in which functions, which were previously implemented with a plurality of chips in the past, are integrated into one chip.
FIG. 4 is a flowchart showing process steps of a proposal of a timing constraint generating method for generating a timing constraint on a higher-level block based on existing timing constraints on lower-level blocks. In FIG. 4, step 41 is a data input step of inputting data on a logic circuit having a hierarchical structure, library data holding primitive information on the logic circuit and timing constraints on lower-level blocks of the logic circuit. Step 42 is a constraint converting step of converting the input constraints on the lower-level blocks into a constraint on the higher-level block.
Procedures according to the timing constraint generating method thus constructed will be described with reference to FIGS. 5 and 6.
FIG. 5 is a flowchart showing the constraint converting step 42 shown in FIG. 4 in detail. FIG. 6 is a diagram showing examples of a logic circuit to which data has been input and timing constraints. In FIG. 6, reference numeral 60 denotes a higher-level block representing a whole logic circuit shown in the drawing. A lower-level block BLKA61 and a lower-level block BLKB62 are at a level immediately below the higher-level block 60. The lower-level block BLKA61 includes a flip-flop 611 and a combinational circuit 612. The lower-level block BLKB62 includes a flip-flop 622 and a combinational circuit 621. The flip-flop 611 in the lower-level block BLKA61 receives a clock CK1 and the flip-flop 622 in the lower-level block BLKB62 receives a clock CK2. A timing constraint 63 is set at a block pin OUT613 of the lower-level block BLKA61. This timing constraint 63 includes an output delay constraint 631 and a multi-cycle constraint 632. A timing constraint 64 is set at a block pin IN623 of the lower-level block BLKB62. This timing constraint 64 includes an input delay constraint 641 and a multi-cycle constraint 642.
Now, a flow of the constraint converting step shown in FIG. 5 will be described with reference to FIG. 6.
First, at step 51, a timing constraint on a lower-level block is extracted. Then, at step 52, it is determined whether the extracted timing constraint is an object of conversion or not. For example, in the logic circuit shown in FIG. 6, if the extracted timing constraint is the output delay constraint 631, this extracted timing constraint is determined to be unnecessary for the higher-level block whereas if the extracted timing constraint is the multi-cycle constraint 632, this constraint is determined to be necessary. In the case of the determination to be an object of conversion, a set point at which the extracted timing constraint is set is switched from a point in the lower-level block to a point in the higher-level block at step 53. For example, a set point for the multi-cycle constraint 632 is changed from “OUT” in the lower-level block to a “BLKA/OUT” in the higher-level block.
On the other hand, in the case of the determination not to be an object of conversion at step 52, it is determined whether all the timing constraints are extracted or not at step 54. If one or more timing constraints have not been extracted yet, the process returns to step 51. After all the timing constraints have been extracted, at least one converted timing constraint is output at step 55. This converted timing constraint is a timing constraint on the higher-level block 60 as shown in FIG. 7, for example. Specifically, the set point is switched in such a manner that “mcp 2—to OUT”, i.e., the multi-cycle constraint 632 in the timing constraint 63 which has been set at the block pin OUT613 of the lower-level block BLKA61 shown in FIG. 6, is changed into “mcp 2—through BLKA/OUT” shown in FIG. 7. Then, “mcp 2—through BLKA/OUT” is output as a timing constraint on the higher-level block. The same holds for the timing constraint 64 at the block pin IN623 of the lower-level block BLKB62.
In the timing constraint generating method as described above, however, if an extracted timing constraint is a timing constraint on a lower-level block and reflected as a timing constraint on a higher-level block, e.g., the multi-cycle constraint as described above, multi-cycle constraints on lower-level blocks are used as a timing constraint on a higher-level block without change, though the clocks CK1 and CK2 referred to by the respective two lower-level blocks 61 and 62 shown in FIG. 6 differ from each other and do not match each other. That is, the matching between interface specifications of the lower-level blocks at the same level is not taken into consideration in this way. Accordingly, if a timing constraint on a higher-level block is generated based on timing constraints on a plurality of lower-level blocks exhibiting no matching, the timing constraint on the higher-level block might be too reduced or too rigorous. In this case, debugging for analyzing an error occurring in interface specifications between the lower-level blocks at the same level is needed or there arises a drawback in which timing designs for the lower-level blocks need to be performed again because circuit specifications are not satisfied.